Analog Devices ADN2812 Manuals

ManualLib has 4 documents for the Analog Devices ADN2812: 3 datasheets. Every file can be read online or downloaded as a PDF for free.

Datasheet 3

Key facts

Model
ADN2812
Industry
Electronics
Documents
4
Languages
EN
Last added
2012-08-02

Start here

Analog Devices AN-746 ADN2812 FDDI Support Application Note

Analog Devices AN-746 ADN2812 FDDI Support Application Note

Application Note 4 pages · 76 KB · EN

The document describes the limitations of the ADN2812's default 'lock to data' operating mode when supporting the FDDI connection protocol. Specifically, it details how non-random bit patterns in the FDDI PCM states (Break, Connect, Next) cause frequency acquisition issues because they lack sufficient transitions at the target 125 Mbps rate.

To resolve this, the note provides a solution using an external reference clock to place the ADN2812 into 'lock to REFCLK' mode. It explains that in this configuration, the device locks its VCO frequency to an external reference rather than relying on data transitions, ensuring stable synchronization through the FDDI initialization sequence.

Read online

Analog Devices ADN2812 specifications

Data Rate12.3 Mb/s to 2.7 Gb/s
Operating Temperature Range-40°C to +85°C
Supply Voltage3.3 V
Supply Current235 mA typical
Package5 mm x 5 mm 32-lead LFCSP
Jitter Generation (OC-48)0.002 UI rms

Source: Analog Devices ADN2812 Datasheet

All Analog Devices ADN2812 documents by type

Application Note 1

How to use the product for one specific task, with worked examples.

Questions answered in these manuals

Why does the ADN2812 fail to support FDDI in its default mode?

The default 'lock to data' mode cannot handle the non-random, repetitive bit patterns (consecutive Q, H, and I symbols) generated during FDDI PCM states, which lack transitions at 125 Mbps.

From: Analog Devices AN-746 ADN2812 FDDI Support Application Note

How is the ADN2812 configured to support FDDI?

It must be programmed into 'lock to REFCLK' mode using an external reference clock, typically a 125 MHz system clock.

From: Analog Devices AN-746 ADN2812 FDDI Support Application Note

Does the ADN2812 require a reference clock?

No, the device automatically locks to all data rates without the need for an external reference clock or programming.

From: Analog Devices ADN2812 Datasheet

What is the typical supply current?

The typical power supply current is 235 mA.

From: Analog Devices ADN2812 Datasheet

What data rates does the ADN2812 support?

It supports continuous data rates from 12.3 Mb/s up to 2.7 Gb/s.

From: Analog Devices ADN2812 Clock and Data Recovery IC Datasheet

What is the supply voltage range for the ADN2812?

The device operates from 3.0 V to 3.6 V, with a typical value of 3.3 V.

From: Analog Devices ADN2812 Clock and Data Recovery IC Datasheet