Key facts
- Brand
- Analog Devices
- Model
- AD1891
- Category
- Other Electronics
- Documents
- 3
- Languages
- EN
- Last added
- 2012-08-02
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Analog Devices AN-399 Interfacing AD1890/AD1891 to AES Receivers
This document addresses sample rate interfacing and compatibility issues between the AD1890/AD1891 Asynchronous Sample Rate Converter (ASRC) and digital audio components using the AES/EBU (AES3-199X) and IEC-958 standards. It specifically examines the challenges of connecting components that use different data justification formats (right-justified vs. left-justified).
Read onlineAnalog Devices AD1891 specifications
| Dynamic Range (AD1890) | 120 dB |
|---|---|
| Dynamic Range (AD1891) | 96 dB |
| Supply Voltage (VDD) | 2.7 V – 5.5 V |
| Supply Current (VDD = 5.0 V) | 35 mA – 40 mA |
| Sample Clock Frequency Range | 8 kHz – 56 kHz |
| Clock Ratio | 1:2 – 2:1 |
| Input Word Width (AD1890) | 4 – 20 bits |
Source: Analog Devices AD1890/AD1891 SamplePort Stereo Asynchronous Sample Rate Converter Datasheet
All Analog Devices AD1891 documents by type
How to use the product for one specific task, with worked examples.
Ratings, dimensions and ordering codes, for selection and design work.
Questions answered in these manuals
What is the standard for interfacing digital audio components in the digital domain?
The AES/EBU AES3-199X and the IEC-958 have become the standard for interfacing digital audio components in the digital domain.
From: Analog Devices AN-399 Interfacing AD1890/AD1891 to AES Receivers
How can data justification be changed from right-justified to left-justified?
Data justification can be changed by delaying the L/R clock outputted by the receiver chip by the word clock, effectively changing the data to left justification.
From: Analog Devices AN-399 Interfacing AD1890/AD1891 to AES Receivers
What is the supply voltage range for the AD1890/AD1891?
The devices operate from a VDD of 2.7 V to 5.5 V.
From: Analog Devices AD1890/AD1891 SamplePort Stereo Asynchronous Sample Rate Converter Datasheet
How much sample‑clock jitter can the AD1890/AD1891 tolerate?
The input and output sample‑clock jitter tolerance is up to 10 ns for less than 1 dB degradation in THD+N.
From: Analog Devices AD1890/AD1891 SamplePort Stereo Asynchronous Sample Rate Converter Datasheet
What is the input sample clock frequency range of the AD1890/AD1891?
The devices accept input sample clocks from 8 kHz up to 56 kHz.
From: Analog Devices AD1890/AD1891 SamplePort Asynchronous Sample Rate Converter Datasheet
How many pins are in the DIP package?
The DIP version uses a 28‑lead plastic package.
From: Analog Devices AD1890/AD1891 SamplePort Asynchronous Sample Rate Converter Datasheet