Analog Devices AN-746 ADN2812 FDDI Support Application Note

About this manual

The document describes the limitations of the ADN2812's default 'lock to data' operating mode when supporting the FDDI connection protocol. Specifically, it details how non-random bit patterns in the FDDI PCM states (Break, Connect, Next) cause frequency acquisition issues because they lack sufficient transitions at the target 125 Mbps rate.

To resolve this, the note provides a solution using an external reference clock to place the ADN2812 into 'lock to REFCLK' mode. It explains that in this configuration, the device locks its VCO frequency to an external reference rather than relying on data transitions, ensuring stable synchronization through the FDDI initialization sequence.

What's inside

• Introduction
• FDDI Connection Protocol
• PCM Entities and States
• NRZI Encoding
• ADN2812 Default Mode
• Lock to REFCLK Mode Solution
• Register Configuration

Frequently asked questions

Why does the ADN2812 fail to support FDDI in its default mode?

The default 'lock to data' mode cannot handle the non-random, repetitive bit patterns (consecutive Q, H, and I symbols) generated during FDDI PCM states, which lack transitions at 125 Mbps.

How is the ADN2812 configured to support FDDI?

It must be programmed into 'lock to REFCLK' mode using an external reference clock, typically a 125 MHz system clock.

What register controls the lock-to-reference-clock mode?

The CTRLA register in I2C is used to set the control bits and enable this mode.