Key facts
- Brand
- Analog Devices
- Model
- ADUC7124
- Industry
- Industrial
- Documents
- 2
- Languages
- EN
- Last added
- 2012-08-03
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ANALOG DEVICES ADuC7124/ADuC7126: Precision Analog Microcontroller 12-Bit Analog I/O Large Memory ARM7TDMI MCU with Enhanced IRQ Handler Silicon Anomaly (Rev A 2011-10-25-) Manual
This document serves as a silicon anomaly list for the ADuC7124 and ADuC7126 Precision Analog Microcontrollers, specifically for Revision B silicon branded with the B30 kernel revision. It details known issues and provides recommended workarounds to ensure compatibility with present software and systems while future silicon revisions are developed.
The document is divided into two main sections: Functionality Issues and Performance Issues. Functionality issues cover problems with ADC conversion trigger modes (CONV and PLA edge triggers), I2C slave interface disabling during transfers, SPI slave mode clock pulse requirements, and Timer0 periodic mode operation. Performance issues address limitations regarding ADC and DAC reference selection stability and JTAG clock speed constraints.
Analog Devices ADUC7124 specifications
| Silicon Revision | Revision B |
|---|---|
| Kernel Revision | B30 |
| Internal Reference Voltage | 2.5 V |
| JTAG Clock Limitation | 800 kHz or less |
All Analog Devices ADUC7124 documents by type
Ratings, dimensions and ordering codes, for selection and design work.
Disassembly, diagnostics and part numbers, for repair.
Questions answered in these manuals
What silicon revision does this anomaly list apply to?
This list applies to ADuC7124/ADuC7126 MicroConverter Revision B silicon.
What workaround is recommended for the ADC and DAC reference selection limitation?
Set REFCON = 0x00 for the ADC to use the external reference, and set DACxCON[1:0] = 01 for the DACs to use a different external reference.
What is the ADC sampling rate?
The device provides a 1 MSPS (1 million samples per second) multichannel ADC.
How many UART channels are available?
Two UART channels are provided, each with a 16‑byte FIFO for input and output.