This document is about ADuC7124/ADuC7126 anomalies
This document serves as a silicon anomaly list for the ADuC7124 and ADuC7126 Precision Analog Microcontrollers, specifically for Revision B silicon branded with the B30 kernel revision. It details known issues and provides recommended workarounds to ensure compatibility with present software and systems while future silicon revisions are developed.
The document is divided into two main sections: Functionality Issues and Performance Issues. Functionality issues cover problems with ADC conversion trigger modes (CONV and PLA edge triggers), I2C slave interface disabling during transfers, SPI slave mode clock pulse requirements, and Timer0 periodic mode operation. Performance issues address limitations regarding ADC and DAC reference selection stability and JTAG clock speed constraints.
| Silicon Revision | Revision B |
|---|---|
| Kernel Revision | B30 |
| Internal Reference Voltage | 2.5 V |
| JTAG Clock Limitation | 800 kHz or less |
This list applies to ADuC7124/ADuC7126 MicroConverter Revision B silicon.
Set REFCON = 0x00 for the ADC to use the external reference, and set DACxCON[1:0] = 01 for the DACs to use a different external reference.