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- Brand
- Texas Instruments
- Model
- 54H
- Category
- Chips
- Documents
- 51
- Languages
- EN
- Last added
- 2012-06-05
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54/7421 54H/74H21 54LS/74LS21 handbook
Datasheet 1 pages · 51 KB · EN
This document provides technical specifications for the Dual 4-Input Positive AND Gate, covering both commercial (54/74) and military (54H/74H) grade devices. It includes connection diagrams for various package types such as Plastic DIP, Ceramic DIP, Flatpak, and SOT.
Read onlineTexas Instruments 54H specifications
| Operating Temperature Range | -55 °C to 125 °C |
|---|---|
| Supply Voltage (HC types) | 2 V to 6 V |
| Supply Voltage (HCT types) | 4.5 V to 5.5 V |
| Propagation Delay (HC, CL=50pF) | 200 ns (typ) to 300 ns (max) |
| Input High Voltage (VIH, HC) | 2.0 V (typ) |
Source: Texas Instruments CD54HC173 / CD74HC173 / CD54HCT173 / CD74HCT173 Datasheet
All Texas Instruments 54H documents by type
Datasheet 47
Ratings, dimensions and ordering codes, for selection and design work.
- 54/7421 54H/74H21 54LS/74LS21 handbook 1 p
- Texas Instruments SN54HCT373 & SN74HCT373 Octal Transparent D‑Type Latches 3‑State Outputs Datasheet 6 p
- Texas Instruments CD54HC173 / CD74HC173 / CD54HCT173 / CD74HCT173 Datasheet 17 p
- Texas Instruments CD54HC640 CD74HC640 CD54HCT640 CD74HCT640 High-Speed CMOS Logic Octal Three-State Bus Transceiver Inve 11 p
- Texas Instruments SN54HC573A / SN74HC573A Datasheet 16 p
- Texas Instruments SN54HC163 and SN74HC163 Datasheet 24 p
- Texas Instruments SN54HC03 Datasheet 5 p
- TEXAS INSTRUMENTS CD54HC112 CD74HC112 CD54HCT112 CD74HCT112 Dual J-K Flip-Flop with Set Reset Negative-Edge Trigger handbook 17 p
- TEXAS INSTRUMENTS CD54HC109 CD74HC109 CD54HCT109 CD74HCT109 Dual J-K Flip-Flop with Set Reset Positive-Edge Trigger handbook 15 p
- Texas Instruments SN54HC109 / SN74HC109 Dual J‑K Flip‑Flop Datasheet 17 p
- Texas Instruments CD54HC73 / CD74HC73 / CD74HCT73 Dual J‑K Flip‑Flop with Reset Negative‑Edge Trigger Datasheet 15 p
- Texas Instruments CD54HC107 / CD74HC107 / CD74HCT107 Dual J‑K Flip‑Flop with Reset Datasheet 15 p
- Texas Instruments CD54HC175 CD74HC175 CD54HCT175 CD74HCT175 Datasheet 14 p
- Texas Instruments CD54HC173 CD74HC173 CD54HCT173 CD74HCT173 Datasheet 20 p
- Texas Instruments SN54HC86 / SN74HC86 Datasheet 16 p
- TEXAS INSTRUMENTS CD54HC86 CD74HC86 CD54HCT86 CD74HCT86 High-Speed CMOS Logic Quad 2-Input EXCLUSIVE-OR Gatehandbook 13 p
- TEXAS INSTRUMENTS CD54HC7266 CD74HC7266 High-Speed CMOS Logic Quad 2-Input EXCLUSIVE NOR Gatehandbook 12 p
- Texas Instruments SN54HC266 and SN74HC266 Datasheet 12 p
- Texas Instruments SN54HC7002 / SN74HC7002 Datasheet 13 p
- Texas Instruments SN54HCT02 / SN74HCT02 Quadruple 2-Input Positive-NOR Gate Datasheet 13 p
- Texas Instruments SN54HC7032 / SN74HC7032 Datasheet 12 p
- Texas Instruments CD54HC27, CD74HC27, CD54HCT27, CD74HCT27 Datasheet 13 p
- Texas Instruments SN54HC02 / SN74HC02 Quad 2-Input NOR Gate Datasheet 17 p
- Texas Instruments CD54HC32 CD74HC32 CD54HCT32 CD74HCT32 Datasheet 13 p
- Texas Instruments SN54HC32 / SN74HC32 Datasheet 17 p
- TEXAS INSTRUMENTS CD54HC4075 CD74HC4075 CD54HCT4075 CD74HCT4075 Manual 17 p
- Texas Instruments SN54HCT32 / SN74HCT32 Quadruple 2-Input Positive-OR Gates Data Sheet 14 p
- Texas Instruments SN54HC10 3-Input NAND Gate Datasheet 17 p
- TEXAS INSTRUMENTS SN54HC00 SN74AC00 handbook 17 p
- Texas Instruments SN54HCT08, SN74HCT08 Quadruple 2-Input Positive-AND Gates Datasheet 14 p
- Texas Instruments CD74HC132 CD74HCT132 CD54HC132 CD54HCT132 Data Sheet 14 p
- Texas Instruments SN54HC21 SN74HC21 Dual 4-Input Positive-AND Gates Data Sheet 16 p
- Texas Instruments CD54HC08 / CD74HC08 / CD54HCT08 / CD74HCT08 Datasheet 15 p
- Texas Instruments CD54HC10 CD74HC10 CD54HCT10 CD74HCT10 Datasheet 13 p
- Texas Instruments CD54HC11, CD74HC11, CD54HCT11, CD74HCT11 High-Speed CMOS Logic Triple 3-Input AND Gate Datasheet 13 p
- Texas Instruments SN54HC367 / SN74HC367 Datasheet 15 p
- Texas Instruments SN54HC04 / SN74HC04 Hex Inverter Datasheet 16 p
- Texas Instruments CD54HC297 / CD74HC297 / CD74HCT297 High‑Speed CMOS Logic Digital Phase‑Locked Loop Datasheet 14 p
- Texas Instruments CD54HC85 CD74HC85 CD54HCT85 CD74HCT85 4‑Bit Magnitude Comparator Datasheet 15 p
- TEXAS INSTRUMENTS - CD54HC259 CD74HC259 CD54HCT259 CD74HCT259 High-Speed CMOS Logic 8-Bit Addressable Latch handbook 14 p
- Texas Instruments SN54HC245 SN74HC245 Octal Bus Transceivers with 3-State Outputs Datasheet 16 p
- Texas Instruments CD54HC245 / CD54HCT245 / CD74HC245 / CD74HCT245 Datasheet 7 p
- TEXAS INSTRUMENTS CD54HC4046A CD74HC4046A CD54HCT4046A CD74HCT4046A High-Speed CMOS Logic Phase-Locked Loop with VCO 28 p
- Texas Instruments SN54HC174 & SN74HC174 Hex D-Type Flip-Flops with Clear Datasheet 6 p
- Texas Instruments SN54HC574 / SN74HC574 Datasheet 7 p
- Texas Instruments CD54HC10 / CD74HC10 / CD54HCT10 / CD74HCT10 Triple 3-Input NAND Gate Datasheet 9 p
- Texas Instruments CD54HC14 CD74HC14 CD54HCT14 CD74HCT14 Datasheet 8 p
Other documents 4
- TEXAS INSTRUMETNS CD54HC377 CD74HC377 CD54HCT377 CD74HCT377 Manual
- TEXAS INSTRUMENTS -CD54HC245 CD74HC245 CD54HCT245 CD74HCT245 High-Speed CMOS Logic Octal-Bus Transceiver Three-State Non-Inverting handbook
- TEXAS INSTRUMENTS CD54HC154 CD74HC154 CD54HCT154 CD74HCT154 handbook
- TEXAS INSTRUMENTS -SN54HCT374 SN74HCT374 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS handbook
Questions answered in these manuals
What is the maximum propagation delay for this gate?
The maximum propagation delay is 27 ns under specified conditions.
What temperature range does the SN54HCT373 operate over?
It operates from –55 °C to 125 °C.
What package types are available for the SN54HCT373?
Available packages include plastic small‑outline (DW), standard plastic (N), ceramic flat (W), and others.
What is the operating temperature range for the CD54HC173 family?
The devices operate from –55 °C up to 125 °C.
From: Texas Instruments CD54HC173 / CD74HC173 / CD54HCT173 / CD74HCT173 Datasheet
How is the direction of data flow controlled?
The direction of data flow (A to B or B to A) is controlled by the DIR input.
How are the outputs enabled or disabled?
Outputs are enabled when the Output Enable (OE) input is low; a high OE puts the device in high‑impedance mode.