This document describes the features and characteristics of the Harris Semiconductor SCHS134E chip, including hysteresis on clock inputs for improved noise immunity and increased input rise and fall times, asynchronous reset, complementary outputs, buffered inputs, etc.
The CD54HC73, CD74HC73, and CD74HCT73 are dual J‑K flip‑flops with asynchronous reset and negative‑edge triggering. They offer hysteresis on clock inputs, complementary outputs, buffered inputs, and the ability to drive up to 15 LSTTL loads. The devices are built with silicon‑gate CMOS technology, providing low power consumption while matching LSTTL speed.
The datasheet provides ordering information for several package types (CERDIP, PDIP, SOIC), absolute maximum ratings, operating conditions, detailed DC electrical specifications, switching timing parameters, and mechanical drawings. It also includes test circuits, waveforms, and a notice on handling and warranty.
| Operating Temperature Range | -55°C to 125°C |
|---|---|
| Supply Voltage (HC Types) | 2 V to 6 V |
| Supply Voltage (HCT Types) | 4.5 V to 5.5 V |
The devices operate from –55 °C to +125 °C.
Available packages include CERDIP (14‑lead), PDIP (14‑lead), and SOIC (14‑lead) in various suffixes.