Key facts
- Brand
- Analog Devices
- Model
- ADSP-2126X
- Industry
- Industrial
- Documents
- 12
- Languages
- EN
- Last added
- 2012-08-03
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Analog Devices ADSP-2126x SHARC Processor Hardware Reference
This document serves as a comprehensive hardware reference for the ADSP-2126x SHARC® Processor family. It provides detailed technical information on the processor core, processing elements, program sequence control, and internal buses.
The manual covers specific features of the ADSP-21261, ADSP-21262, ADSP-21266, and ADSP-21267 models. Topics include numeric formats (floating-point and fixed-point), arithmetic logic unit operations, data address generators, memory organization, I/O architecture, and development tools.
Analog Devices ADSP-2126X specifications
| Max CCLK for ADSP-2126x | 200 MHz |
|---|---|
| Max CCLK for ADSP-21368 | 400 MHz |
| Max CCLK for ADSP-2146x | 450 MHz |
| PLL Lock Time | 4096 CCLK cycles |
| Divider Effect Time | 16 CCLK cycles |
| VCO Frequency Formula | fVCO = 2 * PLLM * fINPUT |
Source: Analog Devices SHARC Processors Core PLL Management Application Note
All Analog Devices ADSP-2126X documents by type
Day-to-day operation, settings and troubleshooting. Start here if the product is already set up.
How to use the product for one specific task, with worked examples.
- Analog Devices EE-232 ADSP-2126x SHARC DSP Signal Routing Unit Configuration Guide 6 p
- Analog Devices SHARC Processors Core PLL Management Application Note 14 p
- Interfacing NAND Flash Memory with ADSP-2126x SHARC Processors EE-279 15 p
- Analog Devices EE-220 Using External Memory with ADSP-2126x SHARC DSPs 11 p
- Interfacing MultiMediaCard with ADSP-2126x SHARC Processors Application Note 6 p
- Analog Devices Code Overlays on Third Generation SHARC Processors EE-230 Application Note 14 p
- Analog Devices SHARC Processors In-Circuit Flash Programming Application Note 5 p
- Analog Devices EE-231 In-Circuit Programming of an SPI Flash with SHARC Processors 6 p
- Analog Devices EE-243 Expert DAI for SHARC Processors 9 p
Instruction set, parameters and examples for configuring or programming the device.
Questions answered in these manuals
What is the Signal Routing Unit (SRU) on the ADSP-2126x DSP?
The SRU is a software-controlled matrix that allows engineers to define the function of the 20 pins of the digital audio interface (DAI).
From: Analog Devices EE-232 ADSP-2126x SHARC DSP Signal Routing Unit Configuration Guide
How many unique signals can be connected to the DAI pins?
You can connect 20 or fewer unique signals to the DAI pins, as the SRU allows you to define the function of the 20 pins of the digital audio interface (DAI).
From: Analog Devices EE-232 ADSP-2126x SHARC DSP Signal Routing Unit Configuration Guide
How many cycles does the PLL require to lock?
The PLL requires 4096 CCLK cycles to lock at the programmed frequency.
From: Analog Devices SHARC Processors Core PLL Management Application Note
What is the minimum wait time for new divider values to take effect?
You must wait a minimum of 16 CCLK cycles for the new divider values to take effect.
From: Analog Devices SHARC Processors Core PLL Management Application Note
What is the primary difference between NAND flash and NOR flash?
NAND flash is block accessible, whereas NOR flash is byte accessible.
From: Interfacing NAND Flash Memory with ADSP-2126x SHARC Processors EE-279
Which memory device was used to demonstrate this interface?
The K9F1208U0B manufactured by Samsung Electronics.
From: Interfacing NAND Flash Memory with ADSP-2126x SHARC Processors EE-279