Key facts
- Brand
- Analog Devices
- Model
- ADSP-2146x)
- Category
- Other Electronics
- Documents
- 4
- Languages
- EN
- Last added
- 2012-08-03
Start here
Analog Devices SHARC Processors Core PLL Management Application Note
This document explains how to program the core phase-locked loop (PLL) on ADSP-2126x, ADSP-2136x, ADSP-2137x, ADSP-2146x, ADSP-2147x, and ADSP-2148x SHARC processors. It details the use of the Power Management Control Register (PMCTL) to select core clock (CCLK) to input clock (CLKIN) ratios dynamically in software, offering power savings and flexibility beyond hardware pin limitations. The note includes block diagrams for various processor families illustrating input dividers, multipliers, and output dividers.
Read onlineAnalog Devices ADSP-2146x) specifications
| Max CCLK for ADSP-2126x | 200 MHz |
|---|---|
| Max CCLK for ADSP-21368 | 400 MHz |
| Max CCLK for ADSP-2146x | 450 MHz |
| PLL Lock Time | 4096 CCLK cycles |
| Divider Effect Time | 16 CCLK cycles |
| VCO Frequency Formula | fVCO = 2 * PLLM * fINPUT |
Source: Analog Devices SHARC Processors Core PLL Management Application Note
All Analog Devices ADSP-2146x) documents by type
How to use the product for one specific task, with worked examples.
Questions answered in these manuals
How many cycles does the PLL require to lock?
The PLL requires 4096 CCLK cycles to lock at the programmed frequency.
From: Analog Devices SHARC Processors Core PLL Management Application Note
What is the minimum wait time for new divider values to take effect?
You must wait a minimum of 16 CCLK cycles for the new divider values to take effect.
From: Analog Devices SHARC Processors Core PLL Management Application Note
What signal processing operations do the hardware accelerators implement?
The hardware accelerators implement FIR filters, IIR filters, and FFT operations.
From: Analog Devices ADSP-2146x Hardware Accelerators Application Note
What is the benefit of using hardware accelerators?
They offload the main processor, allowing it to perform general-purpose tasks while the accelerators handle computationally intensive operations.
From: Analog Devices ADSP-2146x Hardware Accelerators Application Note
Which SHARC processor series are supported by this note?
The document covers the ADSP-2126x, ADSP-2136x, ADSP-2137x, and ADSP-2146x families.
From: Analog Devices SHARC Processor Boot Kernel Customization and Firmware Upgradeability EE-345
What is the maximum size of a customized boot kernel?
The length of the customized boot kernel should not exceed 256 instructions.
From: Analog Devices SHARC Processor Boot Kernel Customization and Firmware Upgradeability EE-345