This document introduces the overlay features on Analog Devices SHARC processors family third generation
This document provides technical guidance on managing code overlays in the VisualDSP++ development environment specifically for third-generation SHARC family processors (ADSP-2126x/2136x). It addresses changes required due to the inability of these processors to access 48-bit addresses directly, necessitating special measures for transferring data between external memory and internal overlay blocks.
The note details implementation strategies for storing overlays in various external memory types, including SRAM, parallel EEPROM or Flash, and SPI Flash. It includes specific instructions on using PACKING commands in linker files, handling 48-bit to 32-bit address translations, and configuring the overlay manager for different memory widths.
| Supported Processor Family | Third Generation SHARC (ADSP-2126x/2136x) |
|---|---|
| Internal Memory Size | Between 1 and 3 Mbits total |
The I/O Processor can no longer access 48-bit addresses, so overlays must be copied to equivalent 32-bit locations.
The 48-bit run address is translated into an equivalent 32-bit address by multiplying it by 1.5.