This is a technical note on using Analog Devices DSPs, processors and development tools
This Engineer-to-Engineer Note (EE-220) describes the changes in external memory addressing functionality for the third generation SHARC family of processors, specifically those using the Parallel Port. Unlike previous SHARC DSPs that used an External Port with built-in address translation, the Parallel Port requires physical word addresses and lacks automatic translation, necessitating special software considerations.
| Applicable Processors | ADSP-21261, ADSP-21363, ADSP-21262, ADSP-21364, ADSP-21266, ADSP-21365, ADSP-21267, ADSP-21366, ADSP-21362 |
|---|---|
| Document Revision | Rev 2 |
The Parallel Port no longer accepts logical addresses from the core and requires the physical word address to be supplied to the DMA engine.
No, the Parallel Port does not have the address translation built-in and operates on physical addresses only.
The LDF must include the PACKING() command to enable the linker to generate addresses the Parallel Port can use.