ANALOG DEVICES Managing the Core PLL on SHARC Processors (Rev 5 03/2012) Manual

Update: 28 September, 2023

This document describes how to program the core phase-locked loop (PLL) on ADSP-2126x, ADSP-2136x, ADSP-2137x, ADSP-2146x, ADSP-2147x and ADSP-2148x SHARC® processors. It also provides example code for programming the PLL and discusses possible problems that can occur due to incorrect programming. Lastly, it provides debug techniques for correct PLL handling.

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File format: PDF

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MD5 Checksum: 58540F1F993649E15165EE140BB30197

Publication date: 03 August, 2012

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PDF Link: ANALOG DEVICES Managing the Core PLL on SHARC Processors (Rev 5 03/2012) Manual PDF