This document describes how to program the core phase-locked loop (PLL) on ADSP-2126x, ADSP-2136x, ADSP-2137x, ADSP-2146x, ADSP-2147x and ADSP-2148x SHARC® processors. It also provides example code for programming the PLL and discusses possible problems that can occur due to incorrect programming. Lastly, it provides debug techniques for correct PLL handling.
This document explains how to program the core phase-locked loop (PLL) on ADSP-2126x, ADSP-2136x, ADSP-2137x, ADSP-2146x, ADSP-2147x, and ADSP-2148x SHARC processors. It details the use of the Power Management Control Register (PMCTL) to select core clock (CCLK) to input clock (CLKIN) ratios dynamically in software, offering power savings and flexibility beyond hardware pin limitations. The note includes block diagrams for various processor families illustrating input dividers, multipliers, and output dividers.
| Max CCLK for ADSP-2126x | 200 MHz |
|---|---|
| Max CCLK for ADSP-21368 | 400 MHz |
| Max CCLK for ADSP-2146x | 450 MHz |
| PLL Lock Time | 4096 CCLK cycles |
| Divider Effect Time | 16 CCLK cycles |
| VCO Frequency Formula | fVCO = 2 * PLLM * fINPUT |
The PLL requires 4096 CCLK cycles to lock at the programmed frequency.
You must wait a minimum of 16 CCLK cycles for the new divider values to take effect.
The VCO frequency is calculated as fVCO = 2 * PLLM * fINPUT.