Interfacing NAND Flash Memory with ADSP-2126x SHARC Processors EE-279

This document describes how to interface Analog Devices ADSP-2126x SHARC® processors to NAND Flash memories

Brand: Analog Devices
Category: Memory
Document type: Application Note
Language: English
Pages: 15
File format: PDF
File size: 1.1 MB
Published: 03 August, 2012
Updated: 30 September, 2023
Model: ADSP-2126X
MD5 checksum: 898083607DE8F202688678B16C09380C
PDF: Interfacing NAND Flash Memory with ADSP-2126x SHARC Processors EE-279 PDF

About this manual

NAND flash provides a cost-effective alternative to hard drives for portable and handheld systems, offering higher density than NOR flash. This document details the hardware interface required to connect NAND flash memory to ADSP-2126x SHARC processors, which lack a dedicated on-chip NAND controller.

The guide explains that because the ADSP-2126x parallel port has multiplexed address and data signals without dedicated memory select strobes, an indirect I/O-like interface is necessary. The document provides code examples validated on an EZ-KIT Lite evaluation system using a Samsung K9F1208U0B NAND flash device to demonstrate the implementation.

What's inside

Introduction
NAND Flash versus NOR Flash
Overview of the ADSP-2126x Processor's Parallel Port
K9F1208U0B NAND Flash Specifications
NAND Flash Interface Signals
Flash Commands Overview
READ Operation Procedure

Specifications

Memory Configuration	64M x 8-bit
Supply Voltage Ranges	1.8V, 2.7V, and 3.3V
Program Time (Typical)	200 us per page
Erase Time (Typical)	2 ms per block
Read Cycle Time	50 ns per byte
Page Size	528 bytes

Frequently asked questions

What is the primary difference between NAND flash and NOR flash?

NAND flash is block accessible, whereas NOR flash is byte accessible.

Which memory device was used to demonstrate this interface?

The K9F1208U0B manufactured by Samsung Electronics.

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