Key facts
- Brand
- Analog Devices
- Model
- ADSP-2137X
- Industry
- Industrial
- Documents
- 10
- Languages
- EN
- Last added
- 2012-08-03
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ANALOG DEVICES ADSP-2137x SHARC Processor Hardware Reference (includes ADSP-21367 ADSP-21368 ADSP-21369 ADSP-21371 ADSP-21375) (Revision 2.1 May 2010) Manual
This document serves as a hardware reference for the ADSP-2137x family of SHARC® processors, which includes models ADSP-21367, ADSP-21368, ADSP-21369, ADSP-21371, and ADSP-21375. It provides detailed technical information on the processor's architectural overview, including the core, I/O peripherals, and T/O processor.
Read onlineAnalog Devices ADSP-2137X specifications
| Max CCLK for ADSP-2126x | 200 MHz |
|---|---|
| Max CCLK for ADSP-21368 | 400 MHz |
| Max CCLK for ADSP-2146x | 450 MHz |
| PLL Lock Time | 4096 CCLK cycles |
| Divider Effect Time | 16 CCLK cycles |
| VCO Frequency Formula | fVCO = 2 * PLLM * fINPUT |
Source: Analog Devices SHARC Processors Core PLL Management Application Note
All Analog Devices ADSP-2137X documents by type
Day-to-day operation, settings and troubleshooting. Start here if the product is already set up.
Instruction set, parameters and examples for configuring or programming the device.
How to use the product for one specific task, with worked examples.
- Analog Devices EE-069 Understanding and Using Linker Description Files on SHARC Processors Application Note 7 p
- Analog Devices SHARC Processors Core PLL Management Application Note 14 p
- Analog Devices External Port DMA Modes of Operation for SHARC Processors EE-84 7 p
- Analog Devices SHARC Processors In-Circuit Flash Programming Application Note 5 p
- Analog Devices EE-231 In-Circuit Programming of an SPI Flash with SHARC Processors 6 p
- Analog Devices SHARC Processor Boot Kernel Customization and Firmware Upgradeability EE-345 14 p
- ANALOG DEVICES EE-286 handbook 20 p
- Analog Devices EE-243 Expert DAI for SHARC Processors 9 p
Questions answered in these manuals
What is the purpose of a Linker Description File (.LDF)?
The .LDF file allows programmers to control where specific pieces of code or data reside in a SHARC processor's memory space.
Which SHARC processors does this note apply to?
This EE-Note applies to ADSP-2106x, ADSP-2116x, and ADSP-2137x series processors.
How many cycles does the PLL require to lock?
The PLL requires 4096 CCLK cycles to lock at the programmed frequency.
From: Analog Devices SHARC Processors Core PLL Management Application Note
What is the minimum wait time for new divider values to take effect?
You must wait a minimum of 16 CCLK cycles for the new divider values to take effect.
From: Analog Devices SHARC Processors Core PLL Management Application Note
Which SHARC processors are included in this manual?
The manual includes the ADSP-2136x, ADSP-2137x, and ADSP-214xx SHARC Processors.
What is the part number of this document?
The part number for this programming reference manual is 82-000500-01.