Key facts
- Brand
- Analog Devices
- Model
- ADSP-21262
- Industry
- Industrial
- Documents
- 9
- Languages
- EN
- Last added
- 2012-08-03
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Analog Devices ADSP-21262 SHARC Embedded Processor Handbook
This handbook describes the ADSP-21262 SHARC DSP, a high‑performance 32‑bit/40‑bit floating‑point processor with SIMD architecture. It outlines the core architecture, on‑chip memory, I/O interfaces, and peripheral features such as serial ports, SPI, and the Digital Applications Interface.
The document includes functional block diagrams, pin configurations for BGA and LQFP packages, performance benchmarks, electrical characteristics, and ordering information. It is intended for engineers designing with the ADSP-21262 and for users needing detailed technical data and configuration guidance.
Analog Devices ADSP-21262 specifications
| Core instruction cycle time | 5 ns at 200 MHz (6.6 ns at 150 MHz) |
|---|---|
| On‑chip SRAM | 2 M‑bit dual‑ported |
| On‑chip ROM | 4 M‑bit dual‑ported mask‑programmable |
| DMA channels | 22 zero‑overhead channels |
| Serial ports | Six full‑duplex synchronous ports |
| Maximum core performance | 1200 MFLOPS peak at 200 MHz |
| Parallel port width | 8‑ or 16‑bit |
Source: Analog Devices ADSP-21262 SHARC Embedded Processor Handbook
All Analog Devices ADSP-21262 documents by type
Day-to-day operation, settings and troubleshooting. Start here if the product is already set up.
- ANALOG DEVICES Connecting Character LCD Panels to ADSP-21262 SHARC DSPs Manual
- ANALOG DEVICES Considering the ADSP-21262 SHARC DSP Manual
- ANALOG DEVICES Interfacing the ADSP-21262 SHARC EZ-KIT Lite Boards to High-Speed Converter Evaluation Boards (Rev 1 01/2004) Manual
- ANALOG DEVICES Porting PC-Based MP3 Player Software to ADSP-21262 SHARC Processors Manual
- ANALOG DEVICES ADSP-21262 EZ-KIT Lite Manual (Rev. 3.0 August 2006)
- ANALOG DEVICES ADSP-21262 EZ-KIT Lite manual
- Analog Devices ADSP-21262 SHARC Embedded Processor Handbook 48 p
Ratings, dimensions and ordering codes, for selection and design work.
Questions answered in these manuals
What is the core instruction cycle time of the ADSP-21262?
The core instruction cycle time is 5 ns at 200 MHz (or 6.6 ns at 150 MHz).
From: Analog Devices ADSP-21262 SHARC Embedded Processor Handbook
How many DMA channels are available on the processor?
The ADSP-21262 provides 22 zero‑overhead DMA channels.
From: Analog Devices ADSP-21262 SHARC Embedded Processor Handbook
What is the core instruction rate of the ADSP-21262?
The core instruction rate is 200 MHz.
How many DMA channels does the ADSP-21262 support?
It supports up to 22 DMA channels.