Key facts
- Brand
- Analog Devices
- Model
- ADSP-2136X
- Industry
- Industrial
- Documents
- 12
- Languages
- EN
- Last added
- 2012-08-03
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ANALOG DEVICES ADSP-2136x SHARC Processor Hardware Reference (includes the ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 processors) Revision 2.0 June 2009 Manual
This document is the Hardware Reference for the ADSP-2136x family of SHARC processors, specifically covering the ADSP-21362, ADSP-21363, ADSP-21364, ADSP-21365, and ADSP-21366 models. It provides detailed technical information on the processor's architecture, including the core, I/O processor, and various peripherals such as the Digital Applications Interface (DAI), DMA controller, and serial ports.
The manual serves as a comprehensive guide for developers and designers, detailing register definitions, programming models, interrupt handling, and timing specifications. It includes specific sections on configuring DMA transfers, parallel port operations, and serial port configurations, as well as system design considerations like clock generation and pin assignments.
Analog Devices ADSP-2136X specifications
| Max CCLK for ADSP-2126x | 200 MHz |
|---|---|
| Max CCLK for ADSP-21368 | 400 MHz |
| Max CCLK for ADSP-2146x | 450 MHz |
| PLL Lock Time | 4096 CCLK cycles |
| Divider Effect Time | 16 CCLK cycles |
| VCO Frequency Formula | fVCO = 2 * PLLM * fINPUT |
Source: Analog Devices SHARC Processors Core PLL Management Application Note
All Analog Devices ADSP-2136X documents by type
Instruction set, parameters and examples for configuring or programming the device.
Day-to-day operation, settings and troubleshooting. Start here if the product is already set up.
How to use the product for one specific task, with worked examples.
- Analog Devices SHARC Processors Core PLL Management Application Note 14 p
- Analog Devices ADSP-2136x SHARC Processor Asynchronous Sample Rate Converter Programming Guide 8 p
- Interfacing AD7865 Parallel ADCs to ADSP-2136x SHARC Processors Application Note 7 p
- Analog Devices SHARC Processors In-Circuit Flash Programming Application Note 5 p
- ANALOG DEVICES Programming S/PDIF on ADSP-2136x ADSP-21371 SHARC Processors (Rev 2 08/2007) Manual 14 p
- Analog Devices EE-231 In-Circuit Programming of an SPI Flash with SHARC Processors 6 p
- Analog Devices SHARC Processor Boot Kernel Customization and Firmware Upgradeability EE-345 14 p
- Analog Devices EE-243 Expert DAI for SHARC Processors 9 p
Disassembly, diagnostics and part numbers, for repair.
Questions answered in these manuals
How many cycles does the PLL require to lock?
The PLL requires 4096 CCLK cycles to lock at the programmed frequency.
From: Analog Devices SHARC Processors Core PLL Management Application Note
What is the minimum wait time for new divider values to take effect?
You must wait a minimum of 16 CCLK cycles for the new divider values to take effect.
From: Analog Devices SHARC Processors Core PLL Management Application Note
What is the main application of Sample Rate Converters?
The main application is to change sample rate and clean up audio data from jittery clock sources like S/PDIF receivers.
From: Analog Devices ADSP-2136x SHARC Processor Asynchronous Sample Rate Converter Programming Guide
What type of sample rate converters are implemented in ADSP-21364 processors?
The SRC blocks implemented in ADSP-21364 processors are asynchronous sample rate converters.
From: Analog Devices ADSP-2136x SHARC Processor Asynchronous Sample Rate Converter Programming Guide
What interfaces are described for connecting the AD7865 to SHARC processors?
The document describes two schemes: the parallel port interface and the parallel data acquisition port (PDAP) interface.
From: Interfacing AD7865 Parallel ADCs to ADSP-2136x SHARC Processors Application Note
How many channels does the AD7865 support?
The device supports four simultaneous sampling channels.
From: Interfacing AD7865 Parallel ADCs to ADSP-2136x SHARC Processors Application Note