Texas Instruments CDC2516 Manuals

The CDC2516 3.3-V Phase-Lock Loop Clock Driver is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback output (FBOUT) to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDC2516 operates at 3.3-V VCC and provides integrated series-damping resistors that make it ideal for driving point-to-point loads. Four banks of four outputs provide 16 low-skew, low-jitter copies of the input clock. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at the input clock. Each bank of outputs can be enabled or disabled separately via the 1G, 2G, 3G, and 4G control inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the CDC2516 does not require external RC network.

The CDC2516 is a 3.3V phase-lock loop clock driver for synchronous DRAM applications. It distributes one clock input to four banks of four outputs, with separate output enable for each output bank. The external feedback pin (FBIN) is used to synchronize the outputs to the clock input. The CDC2516 has integrated series-damping resistors on-chip and does not require an external RC network. It operates at 3.3V VCC and is packaged in a plastic 48-pin thin shrink small-outline package.