STMicroelectronics M48T58 Manuals

We have 3 manuals for the STMicroelectronics M48T58: 2 Datasheets, 1 User Manual. Free to view online or download as PDF.

STMicroelectronics M48T58 manuals

ST M48T58 M48T58Y 5.0 V 64 Kbit (8 Kb x 8) TIMEKEEPER SRAM handbook

Datasheet

The document describes the features and characteristics of the M48T58 and M48T58Y products, including integrated ultra low-power SRAM, real-time clock, power-fail control circuit, and battery. It also includes BCD coded year, month, day, date, hours, minutes, and seconds, frequency test output for real-time clock, automatic power-fail chip deselect and WRITE protection, WRITE protect voltages, self-contained battery and crystal in the CAPHAT™ DIP package, packaging options, and pin and function compatibility with JEDEC standard 8 Kb x 8 SRAMs.

ST M48T58 M48T58Y5.0V 64Kbit(8Kbx8) TIMEKEEPER SRAM handbook

Datasheet

The M48T58 M48T58Y 5.0V, 64 Kbit (8 Kb x 8) TIMEKEEPER® SRAM is a Toshiba integrated ultra low power SRAM, real time clock, power fail control circuit and battery product. The product has BCD coded YEAR, MONTH, DAY, DATE, HOURS, MINUTES and SECONDS; frequency test output for real time clock; automatic power fail chip deselect and write protection; write protection voltage (VPFD=power fail deselect voltage): - M48T58: VCC=4.75 to 5.5V 4.5V≤VPFD≤4.75V - M48T58Y: VCC=4.5 to 5.5V 4.2V≤VPFD≤4.5V. The product uses self-contained battery and crystal SNAPHAT™DIP package, including 28-lead SOIC and SNAPHAT®TOP (to be ordered separately). SOIC package provides direct connection to a SNAPHAT housing containing the battery and crystal, and is compatible with JEDEC standard 8Kb x 8 SRAM pins and functions.

STMICROELECTRONICS M48T58 M48T58Y Manual

User Manual

M48T58 M48T58Y is a product that integrates ultra-low power SRAM, real-time clock, power-fail control circuit, and battery. It features byte-wide RAM-like clock access, BCD-coded year, month, day, date, hours, minutes, and seconds, frequency test output for real-time clock, and automatic power-fail chip deselect and write protection.