STMicroelectronics STR71x Manuals

ManualLib has 16 documents for the STMicroelectronics STR71x: 14 application notes, 1 datasheet. Every file can be read online or downloaded as a PDF for free.

Application Note 14Datasheet 1

Key facts

Model
STR71x
Documents
16
Languages
EN
Last added
2012-08-09

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ManualST STR71xF handbook

ST STR71xF handbook

This document introduces the Rev 12 1/78 78 STR71xF ARM7TDMI™ 32-bit MCU with Flash, USB, CAN 5 timers, ADC, and 10 communications interfaces, released in February 2008.

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STMicroelectronics STR71x specifications

Number of ADC channelsfour channels (lp1 to |p4 or AINO to AIN3)
Input voltage range0 to 2.5 V
Resolution12-bit format
Maximum sampling frequency1 KHz
Maximum signal frequency500 Hz
Maximum oversampling frequency2.1 MHz

Source: ST AN1798 Application Note

All STMicroelectronics STR71x documents by type

Datasheet 1

Ratings, dimensions and ordering codes, for selection and design work.

Other documents 1

Questions answered in these manuals

What is the maximum value allowed for the UART BR register?

The maximum value for the UART BR register is 65534.

From: STMicroelectronics AN2046 STR71x Clock Configurations Application Note

What is the maximum value allowed for the Watchdog Count Preload Register?

The maximum value for the Watchdog Count Preload Register is 65535.

From: STMicroelectronics AN2046 STR71x Clock Configurations Application Note

What is the primary purpose of this application note?

This document explains how to substitute external EEPROMs with emulated EEPROM using the on-chip Flash of STR71xF devices.

From: STMicroelectronics AN2077 EEPROM Emulation with STR71x Application Note

Which specific microcontroller models does this note mainly refer to?

The content mainly refers to STR710FZ1, STR710FZ2, STR711FR1, STR711FR2, STR712FR2, and STR712FR2.

From: STMicroelectronics AN2077 EEPROM Emulation with STR71x Application Note

When is it possible to initiate a JTAG connection after a system reset?

The JTAG connection sequence cannot be initiated before phase 3 of the flash initialization procedure.

From: STMicroelectronics AN2099 Application Note

How long must a debugger wait after asserting DBGRQ before asserting DBGACK?

The host debugger needs to wait 2048 TCK periods before asserting DBGACK.

From: STMicroelectronics AN2099 Application Note