This EE-286 technical note introduces how to connect SDRAM memory to SHARC® processors.
This document provides technical notes on using Analog Devices DSPs and processors, specifically focusing on interfacing SDRAM memories to SHARC processors. It covers third generation (ADSP-21368, ADSP-2137x) and fourth generation (ADSP-214xx) SHARC processors, detailing their support for SDRAM controllers and differences between generations. The guide discusses glueless interfaces to various SDRAM memory devices, shared memory features, and execution from external memory.
| Supported SDRAM sizes | 32-Mbit, 64-Mbit, 128-Mbit, 256-Mbit, and 512-Mbit |
|---|---|
| SDRAM configurations | x4, x8, x16, and x32 |
| SDC clock speed (ADSP-21368) | 166 MHz |
| SDC clock speed (ADSP-2137x) | 133 MHz |
| SDC clock speed (ADSP-214xx) | 133 MHz or 166 MHz |
The guide covers third generation ADSP-21368, ADSP-2137x and fourth generation ADSP-214xx SHARC processors.
The SDC supports different page sizes that are programmable with column address widths.
Yes, ADSP-214xx processors support direct DMA from SPORT to SDRAM memory, reducing DMA cycles.