Key facts
- Brand
- Analog Devices
- Model
- ADSP-21365
- Industry
- Industrial
- Documents
- 4
- Languages
- EN
- Last added
- 2012-08-03
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ANALOG DEVICES ADSP-2136x SHARC Processor Hardware Reference (includes the ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 processors) Revision 2.0 June 2009 Manual
This document is the Hardware Reference for the ADSP-2136x family of SHARC processors, specifically covering the ADSP-21362, ADSP-21363, ADSP-21364, ADSP-21365, and ADSP-21366 models. It provides detailed technical information on the processor's architecture, including the core, I/O processor, and various peripherals such as the Digital Applications Interface (DAI), DMA controller, and serial ports.
The manual serves as a comprehensive guide for developers and designers, detailing register definitions, programming models, interrupt handling, and timing specifications. It includes specific sections on configuring DMA transfers, parallel port operations, and serial port configurations, as well as system design considerations like clock generation and pin assignments.
Analog Devices ADSP-21365 specifications
| Maximum PDAP clock rate | 50 MHz |
|---|---|
| Maximum data bandwidth | 1 Gbps |
| PDAP data pins | 20 |
| PDAP FIFO depth | 6-deep |
| EBIU data bus width | 16 bits |
Source: Analog Devices EE-254 Interfacing ADSP-21365 PDAP to ADSP-BF533 EBIU
All Analog Devices ADSP-21365 documents by type
Day-to-day operation, settings and troubleshooting. Start here if the product is already set up.
Ratings, dimensions and ordering codes, for selection and design work.
How to use the product for one specific task, with worked examples.
Questions answered in these manuals
What format is used for the PDAP to EBIU interface?
The interface uses the PDAP in 2x16-bit format because the EBIU is 16 bits wide.
From: Analog Devices EE-254 Interfacing ADSP-21365 PDAP to ADSP-BF533 EBIU
Which interrupt signal is used for the handshake protocol?
The interface uses the IRQ0 signal as an edge-sensitive interrupt.
From: Analog Devices EE-254 Interfacing ADSP-21365 PDAP to ADSP-BF533 EBIU
What is the maximum core instruction rate?
The processors are available with up to 333 MHz core instruction rate.
Does the processor support S/PDIF?
Yes, it includes an S/PDIF-compatible digital audio receiver/transmitter.
Which processors are covered in this manual?
The manual covers the ADSP-21362, ADSP-21363, ADSP-21364, ADSP-21365, and ADSP-21366 processors.
What is the document revision?
The document is Revision 2.0.