Key facts
- Brand
- Analog Devices
- Model
- ADSP-2106x SHARC
- Category
- Other Electronics
- Documents
- 3
- Languages
- EN
- Last added
- 2012-08-03
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Analog Devices ADSP-2106x SHARC Processor User Manual
This manual introduces the ADSP-2106x SHARC® processor family, describing its core architecture, computation units, program sequencing, data addressing, and memory organization. It includes chapters on DMA controller features, multiprocessing architectures, host interface timing, and link‑port operation.
The document also covers development tools, booting options, clock specifications, and programming considerations such as floating‑point operations, register usage, and interrupt handling, offering engineers the technical details needed to design and program systems based on the ADSP-2106x.
Analog Devices ADSP-2106x SHARC specifications
| Supported Processor Family | ADSP-2106x SHARC processors |
|---|---|
| Boot Memory Width | single 8-bit-wide memory device |
| Compatible Flash Example | M29W040B 512-KB flash |
| DMA Channel for Flash | DMA channel 9 |
Source: Analog Devices EE-280 In-Circuit Flash Programming on ADSP-2106x SHARC Processors
All Analog Devices ADSP-2106x SHARC documents by type
How to use the product for one specific task, with worked examples.
Day-to-day operation, settings and troubleshooting. Start here if the product is already set up.
Questions answered in these manuals
What is the purpose of this application note?
This note explains how to place variables and other datatypes into 16-bit, or short-word memory, to allow for a more efficient use of memory.
From: Analog Devices EE-62 Accessing Short Word Memory in C Application Note
What is the memory address range for the alt_dmda segment?
The alt_dmda segment starts at address 0x0007c000 and ends at address 0x0007ffff.
From: Analog Devices EE-62 Accessing Short Word Memory in C Application Note
How is the flash memory interfaced to the processor?
The flash memory must be interfaced to the BMS space of the processor for booting, connecting the address bus, data bus, BMS#, and RD# signals.
From: Analog Devices EE-280 In-Circuit Flash Programming on ADSP-2106x SHARC Processors
Which data lines connect the ADSP-21060/21061/21062 to the flash?
Data lines D23:16 of the processor must be connected to data lines D7:0 of the flash.
From: Analog Devices EE-280 In-Circuit Flash Programming on ADSP-2106x SHARC Processors
What is the delay of the REDY signal when the CS pin is asserted?
The REDY signal is de‑asserted about 10 ns after the CS pin is asserted.
Can the ADSP-2106x interface with external memory asynchronously?
Yes, the processor can interface asynchronously to external memories without using CLKIN.