This document explains the fundamentals of sample rate conversion (SRC) and demonstrates how to program the sample rate converters of ADSP-2136x SHARC® processors.
This Engineer-to-Engineer Note (EE-268) provides technical guidance on programming asynchronous Sample Rate Converters (SRCs) found in the ADSP-2136x family of SHARC processors. It details the fundamentals of SRC technology, distinguishing between synchronous and asynchronous types, and explains the digital implementation involving interpolation filters and zero-order holds.
The document includes specific instructions for configuring the SRC blocks within the ADSP-21364 processor, covering register settings such as serial input formats (I2S, TDM) and sample rate ratios. It provides two real-time code examples demonstrating data transfer between Serial Ports (SPORTs) and SRC blocks to achieve various sample rate conversions.
| Number of SRC blocks | four (SRC0–3) |
|---|---|
| Serial input formats supported | left-justified, I2S, time division multiplexing (TDM), and right-justified 24-, 20-, 18-, and 16-bit serial formats |
The main application is to change sample rate and clean up audio data from jittery clock sources like S/PDIF receivers.
The SRC blocks implemented in ADSP-21364 processors are asynchronous sample rate converters.