ANALOG DEVICES Programming S/PDIF on ADSP-2136x ADSP-21371 SHARC Processors (Rev 2 08/2007) Manual

About this manual

This Engineer-to-Engineer Note provides a basic description of the Sony/Philips Digital Interface (S/PDIF), its frame structure, and instructions on how to program S/PDIF on SHARC ADSP-2136x and ADSP-21371 processors to transmit and receive data. It also details the Precision Clock Generator (PCG) setup required to provide necessary signals for an S/PDIF transmit section.

The document includes code examples demonstrating the programming of the S/PDIF transmit and receive sections, specifically for talk-through and data loopback operations. It covers the S/PDIF transmitter inputs, receiver compliance with standards like IEC-60958 and AES3, and the handling of status control bits in the DIRSTAT register.

What's inside

• Introduction
• Basics of S/PDIF
• S/PDIF Bi-Phase Encoding
• S/PDIF Frame Format
• S/PDIF Transmitter
• S/PDIF Receiver
• S/PDIF Receiver Status Control Bits
• S/PDIF Receiver PLL Lock
• S/PDIF Receiver DTS Frame Sizes

Frequently asked questions

What is the maximum number of DTS frame sizes supported by the on-chip SPDIF receiver?

The on-chip SPDIF receiver supports three specific DTS frame sizes: 256, 512, and 1024.

How does the S/PDIF receiver handle incoming data when there is no stream?

If the input is linear PCM, it performs a soft mute by decrementing the last valid audio sample to zero over 4096 frames.

What happens to the DIR_LOCK bit when the S/PDIF PLL becomes unlocked?

The PLL de-asserts the DIR_LOCK bit whenever there is no input stream.