This document is a technical note on using Analog Devices DSPs, processors, and development tools, specifically focusing on the interface between the ADSP-21365 SHARC® PDAP and the ADSP-BF533 Blackfin® EBIU. The ADSP-21365 processors offer a high-bandwidth input data port (PDAP) for data acquisition from an external device, automatically packing the received data into 32-bit words. The document provides information on technical support and online resources.
This Engineer-to-Engineer Note (EE-254) discusses a hardware interface scheme between the ADSP-21365 SHARC processor's Parallel Data Acquisition Port (PDAP) and the External Bus Interface Unit (EBIU) on an ADSP-BF532 Blackfin processor. The interface utilizes the PDAP in 2x16-bit format to match the 16-bit width of the Blackfin EBIU data bus.
The document details the hardware connection, including the mapping of PDAP signals to the Blackfin's DAI pins and the use of specific GPIO flags and interrupts for a handshake protocol. It explains the data transfer protocol involving a Command Phase and a Data Phase, controlled by software running on both processors.
| Maximum PDAP clock rate | 50 MHz |
|---|---|
| Maximum data bandwidth | 1 Gbps |
| PDAP data pins | 20 |
| PDAP FIFO depth | 6-deep |
| EBIU data bus width | 16 bits |
The interface uses the PDAP in 2x16-bit format because the EBIU is 16 bits wide.
The interface uses the IRQ0 signal as an edge-sensitive interrupt.