Key facts
- Brand
- Analog Devices
- Model
- ADSP-21065L
- Industry
- Industrial
- Documents
- 12
- Languages
- EN
- Last added
- 2022-10-14
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Analog Devices ADSP-21065L SHARC DSP User Manual
This manual describes the features, architecture, and operation of the ADSP-21065L SHARC digital signal processor. It covers computation units, memory organization, DMA controller, interrupt handling, timers, I/O ports, and host interface details.
The document also includes system design guidelines, pin definitions, timing specifications for external memory and SDRAM, and programming considerations for both floating‑point and fixed‑point operations.
Analog Devices ADSP-21065L specifications
| Floating-point performance | 180 MFLOPS |
|---|---|
| On-chip SRAM | 544 Kbits |
| Instruction execution | Single cycle |
| DMA channels | Ten |
| Serial ports | Two receivers and two transmitters |
| Timers | Two programmable |
| General-purpose I/O ports | Twelve |
All Analog Devices ADSP-21065L documents by type
Day-to-day operation, settings and troubleshooting. Start here if the product is already set up.
- Analog Devices ADSP-21065L SHARC User's Manual 24 p
- ANALOG DEVICES EE-244 Interfacing Gated Clocks to ADSP-21065L SHARC Processors Manual
- Analog Devices ADSP-21065L EZ-KIT Lite Evaluation System Manual 91 p
- Analog Devices ADSP-21065L DSP Microcomputer User Manual 44 p
- Analog Devices ADSP-21065L SHARC DSP User Manual 780 p
Ratings, dimensions and ordering codes, for selection and design work.
How to use the product for one specific task, with worked examples.
- Analog Devices EE-127 ADSP-21065L On-Chip SDRAM Controller Technical Notes 48 p
- Analog Devices EE-98 ADSP-21065L External Bus Arbitration Application Note 6 p
- Analog Devices Implementing In-Place FFTs on SISD SIMD SHARC Processors Application Note 4 p
- Analog Devices ADSP-21065L EPROM Booting Technical Note 3 p
- Interfacing I2S-Compatible Audio Devices to the ADSP-21065L Serial Ports Application Note 37 p
Instruction set, parameters and examples for configuring or programming the device.
Questions answered in these manuals
What applications is the ADSP-21065L designed for?
It is designed for communications, digital audio, and industrial instrumentation applications.
What is the maximum floating-point performance of the processor?
The processor features a high-performance core capable of 180 MFLOPS.
What is the maximum clock frequency for the SDCLK?
The maximum clock frequency for the SDCLK is 66 MHz.
From: Analog Devices EE-127 ADSP-21065L On-Chip SDRAM Controller Technical Notes
Does the ADSP-21065L support auto precharge?
No, auto precharge is not allowed for this controller.
From: Analog Devices EE-127 ADSP-21065L On-Chip SDRAM Controller Technical Notes
What is the minimum number of ADSP-21065L processors that require an external bus arbiter?
An external bus arbiter is necessary when more than two ADSP-21065L are required to meet real-time specifications.
From: Analog Devices EE-98 ADSP-21065L External Bus Arbitration Application Note
How many input pins does the programmable logic device need to monitor all BR 2 pins for a four-processor cluster?
The design requires four input pins to monitor all BR 2 pins of the connected ADSP-21065L processors.
From: Analog Devices EE-98 ADSP-21065L External Bus Arbitration Application Note