Analog Devices ADSP-21161N Manuals

This document describes how to import code overlays from ROM for use in systems with tight memory constraints.

Introduces how to configure the AD74111 audio codec and connect it to the ADSP-21161 SHARC® DSP

This EE-note explains the functional operation and usage of the ADSP-21161N SHARC® processor asynchronous host interface for uni-processor- and multi-processor systems.

This document is the user manual for EZ-KIT Lite evaluation system, which introduces the hardware, software and usage of the system.

Introduces the features and characteristics of the ADSP-21161N EZ-KIT Lite evaluation system

This document is a technical note on using Analog Devices' DSP components and development tools, specifically focusing on the ADSP-21161N SHARC® DSP chip and its on-chip SDRAM controller. It provides information on the internal signal chain, address-mapping scheme, command truth table, power up sequence, code execution, and timing overview for different access modes. The on-chip SDRAM controller is a hardware intensive solution for addressing SDRAM with a DSP.

The SHARC processor is a high-performance 32-bit DSP used in applications such as audio, medical, military, wireless communications, graphics, imaging, motor control, and telephony. It features a Super Harvard Architecture with four independent buses for dual data fetch, instruction fetch, and nonintrusive zero-overhead I/O. The processor is code compatible with all other SHARC family DSPs and employs a single-instruction multiple-data (SIMD) computational architecture with two 32-bit IEEE floating-point computation units, each equipped with a multiplier, ALU, shifter, and register file. The serial ports support I2S via 8 programmable and simultaneous receive or transmit pins, allowing for up to 16 transmit or 16 receive channels of audio. Integrated peripherals include an integrated I/O processor and 1m bit on-chip dual-ported memory.