This document introduces the new features of the ADSP-21065L chip, including the serial ports and I2S mode functionality. Two I2S loopback examples are also provided.
The document introduces the ADSP-21065L, a first-generation SHARC member supporting 32-bit processing. It details the addition of an I2S mode for its serial ports (SPORT0 and SPORT1), enabling a simple glueless interface to industry-standard audio devices like ADCs and DACs.
The note provides a tutorial on the Philips-developed I2S bus protocol, explaining the timing and data format for transmitting stereo PCM digital data. It describes how the DSP's four transmit and receive pins support up to eight commercial I2S stereo devices, yielding 16 audio channels with only two serial ports.
| On-chip serial ports | SPORT0 and SPORT1 |
|---|---|
| Receive inputs with I2S support | 4 RX Inputs |
| Transmit outputs with I2S support | 4 TX Outputs |
| Input audio channels supported | 8 Input Audio Channels |
| Output audio channels supported | 8 Output Audio Channels |
It is a popular 3 wire serial bus standard protocol developed by Philips for transmission of 2 channel (stereo) Pulse Code Modulation digital data.
The device provides I2S serial port support for interfacing to up to 8 commercially available I2S stereo devices, yielding 16 channels of audio.
No, its built-in support for the I2S protocol eliminates the need for interface logic with a FPGA.