ADSP-21065L is a high-performance signal computer for communications, audio, automotive, instrumentation, and industrial applications. It features a Super Harvard Architecture Computer (SHARC®) with four independent buses for dual data, instruction, and I/O fetch on a single cycle. It supports 32-bit fixed-point arithmetic, 32-bit and 40-bit floating-point arithmetic. The product has 544 Kbits of on-chip SRAM memory and integrated I/O peripheral with I2S support for eight simultaneous receive and transmit channels. It offers 66 MIPS, 198 MFLOPS peak, and 132 MFLOPS sustained performance. It also includes user-configurable 544 Kbits on-chip SRAM memory, two external port DMA channels, eight serial port DMA channels, SDRAM controller, and more.
This manual describes the ADSP-21065L high‑performance signal processor, its architecture, key features, and typical applications in communications, audio, automotive, instrumentation and industrial fields. It includes performance data such as 66 MIPS, 198 MFLOPS peak, and 544 Kbits on‑chip SRAM.
The document also contains detailed pin‑type tables, DMA channel information, SDRAM controller details, ordering guide with package options (208‑lead MOFP or 196‑ball Mini‑BGA), and revision history for the device.
| Peak Performance | 198 MFLOPS |
|---|---|
| On‑Chip SRAM | 544 Kbits |
| Operating Voltage | 3.3 V |
| Package Options | 208‑Lead MOFP or 196‑Ball Mini‑BGA |
| External Address Range | 64 M Words |
| Programmable I/O Pins | 12 |
| Timers with Event Capture | Two |
The ADSP‑21065L includes 544 Kbits of on‑chip SRAM memory.
It operates at 3.3 V.
It is offered in a 208‑lead MOFP or a 196‑ball Mini‑BGA package.