This application note introduces the Analog Devices ADSP-21065L multiprocessing system, which can be used with external bus arbitration to group multiple ADSP-21065Ls to meet the needs of high complexity real-time digital signal processing applications.
The document describes a method for interfacing more than two ADSP-21065L SHARC processors to a common external address and data bus using an external bus arbiter. While the processor supports up to two processors with dedicated configuration pins, a cluster of more than two requires external logic to prevent bus conflicts and ensure synchronization after reset.
The note details the bus arbitration protocol, including how processors identify the bus master and update their internal records. It provides a specific design example using a PAL22V10 programmable logic device to monitor BR2 pins and grant bus mastership to processors requiring external access. The document includes pin assignments and Boolean equations for a state machine that supports both fixed and rotating priority arbitration schemes.
An external bus arbiter is necessary when more than two ADSP-21065L are required to meet real-time specifications.
The design requires four input pins to monitor all BR 2 pins of the connected ADSP-21065L processors.
The design cannot fit into a 20V8 and instead requires the use of a 22V10 device.