Key facts
- Brand
- Fairchild
- Model
- 74F11
- Category
- Other Electronics
- Documents
- 4
- Languages
- EN
- Last added
- 2012-08-07
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Fairchild Semiconductor 74F114 Dual JK Flip-Flop Datasheet
This document is a technical datasheet for the Fairchild Semiconductor 74F114, which contains two high-speed JK flip-flops featuring common Clock and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock, while asynchronous set and clear functions allow independent control of outputs regardless of the clock signal.
The datasheet provides comprehensive electrical characteristics for both DC and AC operating conditions at supply voltages of +5.0V and +8.0V. It includes absolute maximum ratings, logic symbols, connection diagrams, truth tables, and physical dimensions for available packages: the 14-Lead Small Outline Integrated Circuit (SOIC) and the 14-Lead Plastic Dual-In-Line Package (PDIP).
Fairchild 74F11 specifications
| Supply Voltage (Recommended) | +4.5V to +5.5V |
|---|---|
| Operating Temperature Range | 0°C to +70°C |
| Maximum Clock Frequency (at Vcc=+8.0V) | 75 MHz |
| Setup Time (HIGH or LOW) | 4.0 ns Min |
Source: Fairchild Semiconductor 74F114 Dual JK Flip-Flop Datasheet
All Fairchild 74F11 documents by type
Ratings, dimensions and ordering codes, for selection and design work.
Questions answered in these manuals
What is the function of the Clear and Set inputs?
A LOW signal on Sp prevents clocking and forces Q to a HIGH level, while a LOW signal on Cp forces Q to a LOW level.
From: Fairchild Semiconductor 74F114 Dual JK Flip-Flop Datasheet
How are the flip-flops triggered?
Synchronous state changes are initiated by the falling edge of the clock, and triggering occurs at a voltage level not directly related to transition time.
From: Fairchild Semiconductor 74F114 Dual JK Flip-Flop Datasheet
How does the 74F113 transfer data to outputs?
Input data is transferred to the outputs on the falling edge of the clock pulse.
What happens when the asynchronous Set input is LOW?
A LOW input to Sb sets Q to a HIGH level, independent of the clock.
What type of flip-flop is the 74F112?
It is a dual JK negative edge-triggered flip-flop.
From: Fairchild Semiconductor 74F112 Dual JK Flip-Flop Datasheet
How are state changes initiated in this device?
Synchronous state changes are initiated by the falling edge of the clock.
From: Fairchild Semiconductor 74F112 Dual JK Flip-Flop Datasheet