This manual describes the features and functions of the Analog Devices ADSP-2106x SHARC processor.
This manual introduces the ADSP-2106x SHARC® processor family, describing its core architecture, computation units, program sequencing, data addressing, and memory organization. It includes chapters on DMA controller features, multiprocessing architectures, host interface timing, and link‑port operation.
The document also covers development tools, booting options, clock specifications, and programming considerations such as floating‑point operations, register usage, and interrupt handling, offering engineers the technical details needed to design and program systems based on the ADSP-2106x.
| Supported word sizes | 32‑bit and 48‑bit |
|---|---|
| External memory interface mode | Asynchronous, without reference to CLKIN |
| REDY signal de‑assertion delay | approximately 10 ns |
The REDY signal is de‑asserted about 10 ns after the CS pin is asserted.
Yes, the processor can interface asynchronously to external memories without using CLKIN.
It supports both 32‑bit and 48‑bit word formats.