Maxim 500MSPS Manuals

We have 5 manuals for the Maxim 500MSPS: 5 Datasheets. Free to view online or download as PDF.

Maxim 500MSPS manuals

MAXIM MAX101 500Msps 8-Bit ADC with Track/Hold handbook

Datasheet

The MAX101 is an ECL-compatible ADC with a sampling rate of 500Msps and 8-bit resolution. It accurately digitizes analog signals from DC to 250MHz (Nyquist frequency). The MAX101 is designed using Maxim's proprietary advanced bipolar processes and features a high-performance T/H amplifier and two quantizers. The innovative design of the internal T/H ensures an exceptionally wide 1.2GHz input bandwidth and aperture delay uncertainty of less than 2ps, resulting in a high 7.0 effective bits at the Nyquist frequency. Special comparator output design and decoding circuitry reduce out-of-sequence code errors. The probability of erroneous codes due to metastable states is reduced to less than 1 error per 10^15 clock cycles. Unlike other ADCs that can have errors resulting in false full-scale or zero-scale outputs, the MAX101 keeps the error magnitude to less than 1LSB. The analog input is designed for either differential or single-ended use with a ±270mV range. Sense pins for the reference input allow full-scale calibration of the input range or facilitate ratiometric use. Phase adjustment is available to optimize the relative sampling of the converter halves. Input clock phasing is also available for interleaving several MAX101s for higher effective sampling rates.

MAXIM MAX5893 12-Bit 500Msps Interpolating Modulating Dual DAC with CMOS Inputs handbook

Datasheet

The MAX5893 is a programmable interpolating, modulating, 500Msps, dual digital-to-analog converter (DAC) optimized for high-performance wideband, single-carrier transmit applications. It integrates a selectable 2x/4x/8x interpolating filter, a digital quadrature modulator, and dual 12-bit high-speed DACs on a single integrated circuit. At 30MHz output frequency and 500Msps update rate, the in-band SFDR is 84dBc while consuming 1.1W. The device also delivers 72dB ACLR for single-carrier WCDMA at a 61.44MHz output frequency. The selectable interpolating filters allow lower input data rates while taking advantage of the high DAC update rates. These linear-phase interpolation filters ease reconstruction filter requirements and enhance the passband dynamic performance. Individual offset and gain programmability allow the user to calibrate out local oscillator (LO) feedthrough and sideband suppression errors generated by analog quadrature modulators. The MAX5893 features a fIM/4 digital image-reject modulator. This modulator generates a quadrature-modulated IF signal that can be presented to an analog I/Q modulator to complete the upconversion process. A second digital modulation mode allows the signal to be frequency-translated with image pairs at fIM/2 or fIM/4. The MAX5893 features a standard 1.8V CMOS, 3.3V tolerant data input bus for easy interface. A 3.3V SPI™ port is provided for mode configuration.