This document provides a technical overview of the ADSP-21261, ADSP-21262, and ADSP-21266 SHARC DSPs. These devices feature a SIMD computational architecture with two processing elements (PEX and PEY) designed for high-performance audio applications. The processors support code compatibility with previous SHARC families and include integrated on-chip memory and various I/O interfaces.
| Instruction Cycle Time (200 MHz) | 5 ns |
|---|---|
| Instruction Cycle Time (150 MHz) | 6.6 ns |
| Maximum Performance (200 MHz) | 1200 MFLOPS |
| Maximum Performance (150 MHz) | 900 MFLOPS |
| On-Chip SRAM Capacity | Up to 2M bits |
| On-Chip ROM Capacity | Up to 4M bits |
At 200 MHz, the processor performs a 1024 Point Complex FFT in 61.3 us, an FIR Filter per tap in 3.3 ns, and an IIR Filter per biquad in 13.3 ns.
The processors achieve an instruction cycle time of 5 ns at 200 MHz or 6.6 ns at 150 MHz.
The DSPs can perform 1200 MFLOPS running at 200 MHz, or 900 MFLOPS running at 150 MHz.