Analog Devices EE-295 Implementing Delay Lines on SHARC Processors

About this manual

This document discusses the implementation of delay lines on the ADSP-2126x series of SHARC processors, which access external memory via the parallel port. It covers two main techniques: sample-based delay lines using parallel port core access for simple stereo delay effects, and block-based delay lines implemented via parallel port DMA for FIR filters.

What's inside

• Introduction
• Sample-Based Delay Lines
• Block-Based Delay Lines
• Write DMA
• Read DMAs
• Delay process
• Circular Buffering
• FIR Filter implementation

Frequently asked questions

How many external memory locations are required for each tap in the delay line buffer?

Each 32-bit word requires four external memory locations because the external memory is 8 bits wide.

How many cycles does a single 32-bit access via the parallel port require with a PpDUR setting of 3?

A known-duration access requires 15 cycles, calculated as one ALE-cycle plus three CCLKs for setup and four data-cycles times three CCLKs.