SHARC® Embedded Processor ADSP-21262 is a high-performance 32-bit/40-bit floating-point processor with code compatibility, single-instruction multiple-data (SIMD) computational architecture and high-bandwidth I/O.
This handbook describes the ADSP-21262 SHARC DSP, a high‑performance 32‑bit/40‑bit floating‑point processor with SIMD architecture. It outlines the core architecture, on‑chip memory, I/O interfaces, and peripheral features such as serial ports, SPI, and the Digital Applications Interface.
The document includes functional block diagrams, pin configurations for BGA and LQFP packages, performance benchmarks, electrical characteristics, and ordering information. It is intended for engineers designing with the ADSP-21262 and for users needing detailed technical data and configuration guidance.
| Core instruction cycle time | 5 ns at 200 MHz (6.6 ns at 150 MHz) |
|---|---|
| On‑chip SRAM | 2 M‑bit dual‑ported |
| On‑chip ROM | 4 M‑bit dual‑ported mask‑programmable |
| DMA channels | 22 zero‑overhead channels |
| Serial ports | Six full‑duplex synchronous ports |
| Maximum core performance | 1200 MFLOPS peak at 200 MHz |
| Parallel port width | 8‑ or 16‑bit |
The core instruction cycle time is 5 ns at 200 MHz (or 6.6 ns at 150 MHz).
The ADSP-21262 provides 22 zero‑overhead DMA channels.
The processor can achieve a peak of 1200 MFLOPS at 200 MHz.