This document is a technical note on using Analog Devices' DSP components and development tools, specifically focusing on the ADSP-21161N SHARC® DSP chip and its on-chip SDRAM controller. It provides information on the internal signal chain, address-mapping scheme, command truth table, power up sequence, code execution, and timing overview for different access modes. The on-chip SDRAM controller is a hardware intensive solution for addressing SDRAM with a DSP.
This document provides a technical overview of the on-chip SDRAM controller integrated into the ADSP-21161N SHARC DSP. It details the internal signal chain, including the command logic, address buffer, multiplexer, data buffer, and clock divider units designed to handle JEDEC standard SDRAMs.
The guide covers essential aspects of using the controller, such as the command truth table for operations like Read, Write, Precharge, and Refresh. It also explains hardware properties, including interface speed control, address mapping schemes, and specific timing parameters required for reliable operation.
| Maximum SDCLK Frequency | 100 MHz |
|---|---|
| I/O Capability (External) | 32-bit |
| TREF (Row Refresh Period) | 0-0xFFFF |
| TRAS (Active to Precharge) | 1-15 cycles |
The maximum frequency for the synchronous operation clock (SDCLK) is 100 MHz.
No, Power-down mode and Suspend mode are not supported by this controller.