The SHARC processor is a high-performance 32-bit DSP used in applications such as audio, medical, military, wireless communications, graphics, imaging, motor control, and telephony. It features a Super Harvard Architecture with four independent buses for dual data fetch, instruction fetch, and nonintrusive zero-overhead I/O. The processor is code compatible with all other SHARC family DSPs and employs a single-instruction multiple-data (SIMD) computational architecture with two 32-bit IEEE floating-point computation units, each equipped with a multiplier, ALU, shifter, and register file. The serial ports support I2S via 8 programmable and simultaneous receive or transmit pins, allowing for up to 16 transmit or 16 receive channels of audio. Integrated peripherals include an integrated I/O processor and 1m bit on-chip dual-ported memory.
The document describes the ADSP-21161N SHARC processor, a low-cost derivative of the ADSP-21160 designed for high-performance DSP applications. It features Analog Devices' Super Harvard Architecture with four independent buses supporting 32-bit fixed and floating-point formats.
| Core Frequency | 100 MHz or 110 MHz |
|---|---|
| Instruction Cycle Time | 9 ns or 10 ns |
| Peak Performance | Up to 660 MFLOPs |
| On-Chip SRAM | 1M bit dual ported |
| Package Type | 225-ball CSP_BGA |
Yes, it is source code compatible with the ADSP-21160 and first generation ADSP-2106x SHARC processors in SISD mode.
It uses a single-instruction multiple-data (SIMD) architecture with two computational units.