Update: 28 September, 2023
The SHARC processor is a high-performance 32-bit DSP used in applications such as audio, medical, military, wireless communications, graphics, imaging, motor control, and telephony. It features a Super Harvard Architecture with four independent buses for dual data fetch, instruction fetch, and nonintrusive zero-overhead I/O. The processor is code compatible with all other SHARC family DSPs and employs a single-instruction multiple-data (SIMD) computational architecture with two 32-bit IEEE floating-point computation units, each equipped with a multiplier, ALU, shifter, and register file. The serial ports support I2S via 8 programmable and simultaneous receive or transmit pins, allowing for up to 16 transmit or 16 receive channels of audio. Integrated peripherals include an integrated I/O processor and 1m bit on-chip dual-ported memory.
File format: PDF
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MD5 Checksum: 59C5173E3FB98B7A2D3E655CA271B81F
Publication date: 03 August, 2012
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PDF Link: ANALOG DEVICES ADSP-21161N handbook PDF