This EE-note explains the functional operation and usage of the ADSP-21161N SHARC® processor asynchronous host interface for uni-processor- and multi-processor systems.
This document details the functional operation and usage of the asynchronous host interface on the ADSP-21161N SHARC processor. It covers the interface's capabilities in both single-processor and multi-processor systems, including booting procedures and the use of the host loader kernel. The system configuration described involves the ADSP-21161N acting as a slave and the ADSP-21065L emulating a host microprocessor.
| Host Speed | 50 MHz |
|---|---|
| Host bus width | 8, 16, 32 bits |
| Access Timing | asynchr |
| Internal Access | IOP |
The maximum clock speed is 50 MHz, which can be obtained with the CLKOUT pin.
No, the ADSP-21161N acts as a slave, while the ADSP-21065L emulates the host microprocessor.
The interface is present in the ADSP-2106x/M, ADSP-21160M/N, and ADSP-21161N processors.