Maxim MAX510 Manuals

The MAX509/MAX510 are quad, serial-input, 8-bit voltage-output digital-to-analog converters (DACs). They operate with a single +5V supply or dual ±5V supplies. Internal, precision buffers swing rail-to-rail. The reference input range includes both supply rails. The MAX509 has four separate reference inputs, allowing each DAC's full-scale range to be set independently. 20-pin DIP, SSOP, and SO packages are available. The MAX510 is identical to the MAX509 except it has two reference inputs, each shared by two DACs. The MAX510 is housed in space-saving 16-pin DIP and SO packages. The serial interface is double-buffered: A 12-bit input shift register is followed by four 8-bit buffer registers and four 8-bit DAC registers. A 12-bit serial word is used to load data into each register. Both input and DAC registers can be updated independently or simultaneously with single software commands. Two additional asynchronous control pins provide simultaneous updating (LDAC) or clearing (CLR) of input and DAC registers. The interface is compatible with MicrowireTM and SPI/ QSPITM. All digital inputs and outputs are TTL/CMOS compatible. A buffered data output provides for read-back or daisy-chaining of serial devices.

The MAX509/MAX510 are quad, serial-input, 8-bit voltage-output digital-to-analog converters (DACs). They operate with a single +5V supply or dual ±5V supplies. Internal, precision buffers swing rail-to-rail. The reference input range includes both supply rails. The MAX509 has four separate reference inputs, allowing each DAC's full-scale range to be set independently. 20-pin DIP, SSOP, and SO packages are available. The MAX510 is identical to the MAX509 except it has two reference inputs, each shared by two DACs. The MAX510 is housed in space-saving 16-pin DIP and SO packages. The serial interface is double-buffered: A 12-bit input shift register is followed by four 8-bit buffer registers and four 8-bit DAC registers. A 12-bit serial word is used to load data into each register. Both input and DAC registers can be updated independently or simultaneously with single software commands. Two additional asynchronous control pins provide simultaneous updating (LDAC) or clearing (CLR) of input and DAC registers. The interface is compatible with MicrowireTM and SPI/ QSPITM. All digital inputs and outputs are TTL/CMOS compatible. A buffered data output provides for read-back or daisy-chaining of serial devices.