Maxim 170MSPS Manuals

The MAX1122 is a monolithic 10-bit, 170Msps analog-to-digital converter (ADC) optimized for outstanding dynamic performance at high IF frequencies up to 500MHz. The product operates with conversion rates of up to 170Msps while consuming only 460mW. At 170Msps and an input frequency of 100MHz, the MAX1122 achieves a spurious-free dynamic range (SFDR) of 72dBc. Its excellent signal-to-noise ratio (SNR) of 57.5dB at 10MHz remains flat (within 1dB) for input tones up to 500MHz. This makes the MAX1122 ideal for wideband applications such as digital predistortion in cellular base-station transceiver systems. The MAX1122 requires a single 1.8V supply. The analog input is designed for either differential or single-ended operation and can be AC- or DC-coupled. The ADC also features a selectable on-chip divide-by-2 clock circuit, which allows the user to apply clock frequencies as high as 340MHz. This helps to reduce the phase noise of the input clock source. A differential LVDS sampling clock is recommended for best performance. The converter’s digital outputs are LVDS compatible, and the data format can be selected to be either two’s complement or offset binary. The MAX1122 is available in a 68-pin QFN with exposed pad (EP) and is specified over the industrial (-40°C to +85°C) temperature range. For pin-compatible, higher speed versions of the MAX1122, refer to the MAX1123 (210Msps) and the MAX1124 (250Msps) data sheets.

The MAX1213 is a monolithic, 12-bit, 170Msps analog-to-digital converter (ADC) optimized for outstanding dynamic performance at high-IF frequencies up to 300MHz. The product operates with conversion rates up to 170Msps while consuming only 788mW. At 170Msps and an input frequency up to 250MHz, the MAX1213 achieves a spurious-free dynamic range (SFDR) of 72.9dBc. Its excellent signal-to-noise ratio (SNR) of 66.2dB at 10MHz remains flat (within 2dB) for input tones up to 250MHz. This ADC yields an excellent low-noise floor of -68dBFS, which makes it ideal for wideband applications such as cable head-end receivers and power-amplifier predistortion in cellular base-station transceivers. The MAX1213 requires a single 1.8V supply. The analog input is designed for either differential or single-ended operation and can be AC- or DC-coupled. The ADC also features a selectable on-chip divide-by-2 clock circuit, which allows the user to apply clock frequencies as high as 340MHz. This helps to reduce the phase noise of the input clock source. A low-voltage differential signal (LVDS) sampling clock is recommended for best performance. The converter’s digital outputs are LVDS compatible and the data format can be selected to be either two’s complement or offset binary. The MAX1213 is available in a 68-pin QFN package with exposed paddle (EP) and is specified over the industrial (-40°C to +85°C) temperature range. See the Pin-Compatible Versions table for a complete list of part numbers.