Datasheet
The MAX5853 is a dual, 10-bit, 80Msps digital-to-analog converter (DAC) that provides superior dynamic performance in wideband communication systems. The device integrates two 10-bit DAC cores and a 1.24V reference. It supports single-ended and differential modes of operation. The MAX5853 maintains dynamic performance over the entire 2.7V to 3.6V power-supply operating range. The analog outputs support a -1.0V to +1.25V compliance voltage. It can also operate in interleave data mode to reduce the I/O pin count. The MAX5853 features digital control of channel gain matching to within ±0.4dB in sixteen 0.05dB steps, improving sideband suppression in analog quadrature modulation applications. It includes an on-chip 1.24V bandgap reference with a control amplifier for external full-scale adjustments of both channels through a single resistor. The internal reference can be disabled, and an external reference can be applied for high-accuracy applications. The MAX5853 has full-scale current outputs of 2mA to 20mA and operates from a 2.7V to 3.6V single supply. It supports three modes of power-control operation: normal, low-power standby, and complete power-down. In power-down mode, the operating current is reduced to 1µA. The MAX5853 is packaged in a 40-pin thin QFN with exposed paddle (EP) and is specified for the extended (-40°C to +85°C) temperature range.
User Manual
The MAX1209 is a 3.3V, 12-bit, 80Msps analog-to-digital converter (ADC) featuring a fully differential wideband track-and-hold (T/H) input amplifier, driving a low-noise internal quantizer. The analog input stage accepts single-ended or differential signals. The MAX1209 is optimized for low power, small size, and high dynamic performance. Excellent dynamic performance is maintained from baseband to input frequencies of 175MHz and beyond, making the MAX1209 ideal for intermediate-frequency (IF) sampling applications. Powered from a single 3.0V to 3.6V supply, the MAX1209 consumes only 366mW while delivering a typical signal-to-noise (SNR) performance of 66.5dB at an input frequency of 175MHz. In addition to low operating power, the MAX1209 features a 3µW power-down mode to conserve power during idle periods. A flexible reference structure allows the MAX1209 to use the internal 2.048V bandgap reference or accept an externally applied reference. The reference structure allows the full-scale analog input range to be adjusted from ±0.35V to ±1.15V. The MAX1209 provides a common-mode reference to simplify design and reduce external component count in differential analog input circuits. The MAX1209 supports both a single-ended and differential input clock drive. Wide variations in the clock duty cycle are compensated with the ADC’s internal duty-cycle equalizer (DCE). ADC conversion results are available through a 12-bit, parallel, CMOS-compatible output interface.
User Manual
The MAX1208 is a 3.3V, 12-bit, 80Msps analog-to-digital converter (ADC) featuring a fully differential wideband track-and-hold (T/H) input amplifier, driving a low-noise internal quantizer. The analog input stage accepts single-ended or differential signals. The MAX1208 is optimized for low power, small size, and high dynamic performance in baseband applications. Powered from a single 3.0V to 3.6V supply, the MAX1208 consumes only 373mW while delivering a typical signal-to-noise (SNR) performance of 68.2dB at an input frequency of 32.5MHz. In addition to low operating power, the MAX1208 features a 3µW power-down mode to conserve power during idle periods. A flexible reference structure allows the MAX1208 to use the internal 2.048V bandgap reference or accept an externally applied reference. The reference structure allows the full-scale analog input range to be adjusted from ±0.35V to ±1.15V. The MAX1208 provides a common-mode reference to simplify design and reduce external component count in differential analog input circuits. The MAX1208 supports both a single-ended and differential input clock drive. Wide variations in the clock duty cycle are compensated with the ADC’s internal duty-cycle equalizer (DCE). ADC conversion results are available through a 12-bit, parallel, CMOS-compatible output bus. The digital output format is pin selectable to be either two’s complement or Gray code. A data-valid indicator eliminates external components that are normally required to indicate when the ADC is in conversion mode.
