The MAX1208 is a 3.3V, 12-bit, 80Msps analog-to-digital converter (ADC) featuring a fully differential wideband track-and-hold (T/H) input amplifier, driving a low-noise internal quantizer. The analog input stage accepts single-ended or differential signals. The MAX1208 is optimized for low power, small size, and high dynamic performance in baseband applications. Powered from a single 3.0V to 3.6V supply, the MAX1208 consumes only 373mW while delivering a typical signal-to-noise (SNR) performance of 68.2dB at an input frequency of 32.5MHz. In addition to low operating power, the MAX1208 features a 3µW power-down mode to conserve power during idle periods. A flexible reference structure allows the MAX1208 to use the internal 2.048V bandgap reference or accept an externally applied reference. The reference structure allows the full-scale analog input range to be adjusted from ±0.35V to ±1.15V. The MAX1208 provides a common-mode reference to simplify design and reduce external component count in differential analog input circuits. The MAX1208 supports both a single-ended and differential input clock drive. Wide variations in the clock duty cycle are compensated with the ADC’s internal duty-cycle equalizer (DCE). ADC conversion results are available through a 12-bit, parallel, CMOS-compatible output bus. The digital output format is pin selectable to be either two’s complement or Gray code. A data-valid indicator eliminates external components that are normally required to indicate when the ADC is in conversion mode.
The MAX1208 is a 12‑bit, 80 Msps analog‑to‑digital converter optimized for low power, small size, and high dynamic performance. It operates from a single 3.0 V to 3.6 V supply and offers both internal and external reference options, with a configurable full‑scale input range of +0.35 V to +1.15 V.
The device is supplied in a 40‑pin thin QFN package (6 mm × 6 mm × 0.8 mm) with an exposed paddle for heat sinking. Key electrical characteristics include 373 mW typical power consumption in single‑ended mode, 3 µW power‑down current, 68.2 dB SNR, and up to 89.3 dBc SFDR at 3 MHz input.
| Resolution | 12 bits |
|---|---|
| Maximum Sampling Rate | 80 Msps (80 MHz clock) |
| Supply Voltage (analog) | 3.0 V to 3.6 V |
| Digital Supply Voltage | 1.7 V to 3.6 V |
| Typical Power Consumption (single‑ended) | 373 mW |
| Power‑down Current | 3 µW |
| Full‑Scale Input Range | +0.35 V to +1.15 V |
| Package | 40‑pin thin QFN, 6 mm × 6 mm × 0.8 mm, exposed paddle |
In single‑ended clock mode the device consumes about 373 mW.
It is offered in a 40‑pin thin QFN package measuring 6 mm × 6 mm × 0.8 mm with an exposed paddle.
The ADC can sample at up to 80 Msps, driven by an 80 MHz maximum clock frequency.