Key facts
- Brand
- Toshiba
- Model
- TC4027BFN
- Industry
- Industrial
- Documents
- 2
- Languages
- EN
- Last added
- 2012-06-07
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TOSHIBA TC4027BP TC4027BF TC4027BFN handbook(1)
This document is a technical datasheet for the Toshiba TC4027BP, TC4027BF, and TC4027BFN integrated circuits. These devices are CMOS digital integrated circuit silicon monolithic J-K master-slave flip-flops featuring RESET and SET functions.
The datasheet provides maximum ratings, recommended operating conditions, static and dynamic electrical characteristics, logic diagrams, truth tables, and outline drawings for DIP16, SOP16 (200mil), and SOP16 (150mil) packages.
Toshiba TC4027BFN specifications
| Product Type | J-K Master-Slave Flip-Flop |
|---|---|
| Power Dissipation (DIP) | 300 mW |
| Max. Clock Frequency (VDD=5V) | 8.0 MHz |
All Toshiba TC4027BFN documents by type
Ratings, dimensions and ordering codes, for selection and design work.
Questions answered in these manuals
What happens when both RESET and SET inputs are at 'H'?
When both inputs are high, the outputs become Q='H' and Q='H'.
Is the JEDEC SOP (FN) package available for this model?
No, the JEDEC SOP (FN) is not available in Japan.
What happens when both RESET and SET inputs are at 'L'?
The output changes at the rising edge of the clock according to the states of J and K.
What is the typical weight of a DIP16 package?
The typical weight for the DIP16 package is 1.00g.