This document is a technical datasheet for the Toshiba TC4027BP, TC4027BF, and TC4027BFN integrated circuits. It describes these devices as dual J-K master-slave flip-flops featuring RESET and SET functions.
The datasheet provides maximum ratings, recommended operating conditions, static and dynamic electrical characteristics, logic diagrams, truth tables, and package outline drawings for DIP16, SOP16 (200mil), and SOP16 (150mil) packages.
| Product Type | J-K Master-Slave Flip-Flop |
|---|---|
| Power Dissipation (DIP) | 300 mW |
| Max. Clock Frequency (Vcc=5V) | 8.0 MHz |
The output changes at the rising edge of the clock according to the states of J and K.
The typical weight for the DIP16 package is 1.00g.