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This document is a technical datasheet for the Toshiba TC4027BP, TC4027BF, and TC4027BFN integrated circuits. These devices are CMOS digital integrated circuit silicon monolithic J-K master-slave flip-flops featuring RESET and SET functions.
The datasheet provides maximum ratings, recommended operating conditions, static and dynamic electrical characteristics, logic diagrams, truth tables, and outline drawings for DIP16, SOP16 (200mil), and SOP16 (150mil) packages.
| Product Type | J-K Master-Slave Flip-Flop |
|---|---|
| Power Dissipation (DIP) | 300 mW |
| Max. Clock Frequency (VDD=5V) | 8.0 MHz |
When both inputs are high, the outputs become Q='H' and Q='H'.
No, the JEDEC SOP (FN) is not available in Japan.