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Motorola MPC2104P/MPC2105P Secondary Cache Module Datasheet
This document provides technical data for the MPC2104P and MPC2105P, which are 256KB and 512KB BurstRAM secondary cache modules designed for PowerPC PReP and CHRP platforms. These modules utilize synchronous BurstRAMs to provide high-performance L2 cache for the PowerPC 60x microprocessor family.
Read onlineMotorola MPC2104 specifications
| Capacity (MPC2104P) | 256KB |
|---|---|
| Capacity (MPC2105P) | 512KB |
| Configuration (MPC2104P) | 32K x 64 bits |
| Configuration (MPC2105P) | 64K x 64 bits |
| Package Type | 178 pin DIMM |
| Max Clock Rate | 66 MHz |
| Data RAM Access Time | 8 ns |
| Tag RAM Access Time | 9 ns |
Source: Motorola MPC2104P/MPC2105P Secondary Cache Module Datasheet
All Motorola MPC2104 documents by type
Ratings, dimensions and ordering codes, for selection and design work.
Questions answered in these manuals
What are the stated access times for the tag and data RAMs?
The tag RAM has a match access time of 9 ns, and the data RAM has an access time of 8 ns.
From: Motorola MPC2104P/MPC2105P Secondary Cache Module Datasheet
What is the maximum clock rate supported by the module?
The module supports fast clock rates of up to 66 MHz.
From: Motorola MPC2104P/MPC2105P Secondary Cache Module Datasheet
Which microprocessor family are these cache modules designed for?
They are designed for the PowerPC 60x microprocessor family.
What is the pin count for these cache modules?
The modules are configured in a 182-pin DIMM format.