Key facts
- Brand
- Motorola
- Model
- DSP56156
- Documents
- 2
- Languages
- EN
- Last added
- 2012-06-12
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MOTOROLA Semicustom DSP56456 TECHNIAL DATA
The DSP56156 is the first member of Motorola's DSP56100 family of HCMOS, low power, 16-bit general purpose Digital Signal Processors (DSP). Designed primarily for speech coding and telecommunications, it features a built-in sigma-delta voice band codec and phase locked loop (PLL). The processor includes memories, digital peripherals, and provides an off-the-shelf solution with no user programmable ROMs on-chip.
The Central Processing Unit consists of three execution units operating in parallel, allowing up to six operations per instruction cycle. It supports fractional and integer arithmetic, nested hardware DO loops, and zero-overhead fast interrupts. The device operates at frequencies down to DC with a single 5V power supply.
Motorola DSP56156 specifications
| Operating Frequency | 60 MHz |
|---|---|
| Instructions per Second | Up to 30 MIPS |
| Power Supply | Single 5V |
| On-chip Data RAM | 2k x 16-bit |
| On-chip Program RAM | 2k x 16-bit |
| Operating Frequency Range (Codec) | 100KHz to 3MHz |
All Motorola DSP56156 documents by type
Ratings, dimensions and ordering codes, for selection and design work.
Questions answered in these manuals
What is the primary design application for the DSP56156?
It is designed primarily for speech coding and telecommunications.
Does the DSP56156 require off-chip components?
No, it requires no off-chip components.
What is the maximum instruction rate of the DSP56156?
The DSP56156 can execute up to 30 million instructions per second (30 MIPS).
How much on‑chip program RAM does the DSP56156 provide?
It includes 2048 × 16‑bit on‑chip program RAM.