Key facts
- Brand
- Analog Devices
- Model
- ADF4001
- Industry
- Industrial
- Documents
- 2
- Languages
- EN
- Last added
- 2012-05-03
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Analog Devices ADF4001 Clock Generator PLL Datasheet
The ADF4001 is a low‑noise clock generator PLL that includes a digital phase‑frequency detector, precision charge pump, programmable reference divider and a 13‑bit N counter. It supports a 200 MHz output frequency and offers a 3 V to 5.5 V supply range with programmable charge‑pump currents.
The document provides detailed electrical specifications, timing characteristics, pin functions for both TSSOP and LFCSP packages, and typical performance graphs such as phase‑noise and output power. It also includes an ordering guide and recommended ESD handling procedures.
Analog Devices ADF4001 specifications
| Maximum Output Frequency | 200 MHz |
|---|---|
| Supply Voltage Range | 2.7 V to 5.5 V |
| Typical Operating Current | 4.5 mA |
| Phase Noise Floor | –161 dBc/Hz @ 200 kHz |
| RSET Resistor Value | 4.7 kΩ |
| Package Options | 16‑lead TSSOP, 20‑lead LFCSP |
Source: Analog Devices ADF4001 Clock Generator PLL Datasheet
All Analog Devices ADF4001 documents by type
Ratings, dimensions and ordering codes, for selection and design work.
Questions answered in these manuals
What supply voltage range does the ADF4001 support?
The device operates from 2.7 V to 5.5 V supply voltage.
How many pins are available in the TSSOP package?
The TSSOP package has 16 pins.
What is the typical operating current of the ADF4001?
The device draws about 4.5 mA typical operating current.
What is the phase‑noise floor at a 200 kHz PFD frequency?
The phase‑noise floor is –161 dBc/Hz typical at 200 kHz PFD.