Analog Devices AD9520-5 Manuals

AD9520-5 is an AD company's clock generator product. It supports external 3.3V/5V VCO/VCXO to 2.4GHz, supports 1 differential or 2 single-ended reference inputs, supports CMOS, LVDS or LVPECL references to 250MHz, supports 16.67MHz to 33.3MHz crystal reference input, supports optional reference clock doubler, supports reference monitoring function, supports automatic and manual reference switching/holdover mode, supports selectable reverse/non-reverse switching, supports glitch-free reference switching, supports automatic recovery from holdover mode, supports digital or analog lock detection, supports optional zero delay operation, supports 12 1.6GHz LVPECL outputs, each output can be divided into 4 groups, each group of 3 outputs has a 1-to-32 divider with phase delay, output jitter is as low as 225fs rms, the channel-to-channel skew of grouped outputs is less than 16ps, each LVPECL output can be programmed as CMOS or LVPECL output.

The AD9520-5 is a low phase noise, phase-locked loop (PLL) that supports external 3.3 V/5 V VCO/VCXO to 2.4 GHz, 1 differential or 2 single-ended reference inputs, accepts CMOS, LVDS or LVPECL references to 250 MHz, accepts 16.67 MHz to 33.3 MHz crystal for reference input, optional reference clock doubler, reference monitoring capability, automatic and manual reference switchover/holdover modes, with selectable revertive/nonrevertive switching, glitch-free switchover between references, automatic recovery from holdover, digital or analog lock detect, selectable zero delay operation, 12 1.6 GHz LVPECL outputs divided into 4 groups, each group of 3 has a 1 to 32 divider with phase delay, additive output jitter as low as 225 fs rms, channel-to-channel skew grouped outputs <16 ps, each LVPECL output can be configured as differential or single-ended, and the output frequency and phase offset can be selected.